report by Lil Squid from the Noun Project. See:https://thenounproject.com/term/report/149914
  1. [DATE’22] Fan Zhang, Li Yang, Jian Meng, Yu Cao, Jae-sun Seo, and Deliang Fan, “XST: A Crossbar Column-wise Sparse Training for Efficient Continual Learning,” Design, Automation and Test in Europe (DATE), 14 – 23 March 2022 (accept)
  2. [ASPDAC’22]  Fan Zhang, Li Yang, Jian Meng, Yu Cao, Jae-sun Seo, and Deliang Fan, “XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption,”  27th Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 17-20, 2022 (accept)
  3. [HOST’21]  Jingtao Li, Zhezhi He, Adnan Siraj Rakin, Deliang Fan and Chaitali Chakrabarti, “NeurObfuscator: A Full-stack Obfuscation Tool to Mitigate Neural Architecture Stealing,”  In 2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington DC, USA, Dec. 12-15, 2021 (accept) [Archived version]
  4. [ICCAD’21]  Arman Roohi, MohammadReza Taheri, Shaahin Angizi and Deliang Fan, “RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems,”  In 2021 International Conference on Computer Aided Design (ICCAD), Nov. 1-4, 2021
  5. [MASS’21]  Sen Lin, Li Yang, Zhezhi He, Deliang Fan and Junshan Zhang, “MetaGater: Fast Learning of Conditional Channel Gated Networks via Federated Meta-Learning,” In 2021 IEEE 18th International Conference on Mobile Ad Hoc and Smart Systems (MASS), Oct. 4-7, 2021 (Invited) [Archived version]
  6. [USENIX Security’21]  Adnan Siraj Rakin*, Yukui Luo*, Xiaolin Xu and Deliang Fan, “Deep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA,” In 30th USENIX Security Symposium, August 11-13, 2021 (*first two authors contribute equally); [pdf]
  7. [CVPR’21] Li Yang, Zhezhi He, Junshan Zhang and Deliang Fan, “KSM: Fast Multiple Task Adaption via Kernel-wise Soft Mask Learning” IEEE/CVF Computer Vision and Pattern Recognition (CVPR), June 19-25, 2021 [pdf]
  8. [DAC’21] Fan Zhang, Shaahin Angizi and Deliang Fan, “Max-PIM: Fast and Efficient Max/Min Searching in DRAM” In: 58th Design Automation Conference (DAC), San Francisco, CA, Dec. 5-9, 2021 [pdf] ( –Best Paper Nomination–)
  9. [DAC’21] Fan Zhang, Shaahin Angizi, Naima Ahmed Fahmi, Wei Zhang and Deliang Fan, “PIM-Quantifier: A Processing-in-Memory Platform for Genome Quantification”. In: 58th Design Automation Conference (DAC), San Francisco, CA, Dec. 5-9, 2021 [pdf]
  10. [DAC’21] Sai Kiran Cherupally, Adnan Rakin, Shihui Yin, Mingoo Seok, Deliang Fan and Jae-sun Seo. “Leveraging Variability and Aggressive Quantization of In-Memory Computing for Robustness Improvement of Deep Neural Network Hardware Against Adversarial Input and Weight Attacks”. In: 58th Design Automation Conference (DAC), San Francisco, CA, Dec. 5-9, 2021 [pdf]
  11. [GLSVLSI’21] Shaahin Angizi, Arman Roohi, Mohammadreza Taheri and Deliang Fan. “Processing-in-Memory Acceleration of MAC based Applications Using Residue Number System: A Comparative Study,” In 31st edition of Great Lakes Symposium on VLSI (GLSVLSI), June 22-25, 2021 [pdf]
  12. [ISCAS’21] Jian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, Jae-Sun Seo, “Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks,” IEEE International Symposium on Circuits and Systems (ISCAS) (ISCAS), May, 2021 [pdf-journal version]
  13. [IRPS’21] Wangxi He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu, Jae-sun Seo, “Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing,” IEEE International Reliability Physics Symposium, (IRPS), March 21-25, 2021 ( –Best Student Paper Candidate–) [pdf]
  14. [DATE’21] Jingtao Li, Adnan Siraj Rakin, Zhezhi He, Deliang Fan and Chaitali Chakrabarti, “RADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery,” Design, Automation and Test in Europe (DATE), 01-05 Feb. 2021, ALPEXPO, Grenoble, France [pdf]
  15. [ASPDAC’21]  Li Yang, and Deliang Fan, “Dynamic Neural Network to Enable Run-Time Trade-off between Accuracy and Latency,” 26th Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 18-21, 2021 (invited) [pdf]
  16. [SOCC’20]  Li Yang, Zhezhi He, Shaahin Angizi and Deliang Fan, “Processing-In-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency,” 33rd IEEE International System-on-Chip Conference (SOCC), September 8-11, 2020 (invited) [pdf]
  17. [USENIX Security’20]  Fan Yao, Adnan Siraj Rakin and Deliang Fan, “DeepHammer: Depleting the Intelligence of Deep Neural Networks through Targeted Chain of Bit Flips,” In 29th USENIX Security Symposium (USENIX Security 20), August 12-14, 2020, Boston, MA, USA [pdf]  
  18. [ISLPED’20] Mingyen Lee, Wenjun Tang, Bowen Xue, Juejian Wu, Mingyuan Ma, Yu Wang, Yongpan Liu, Deliang Fan, Vijaykrishnan Narayanan, Huazhong Yang and Xueqing Li, “FeFET-Based Low-Power Bitwise Logic-in-Memory with Direct Write-Back and Data-Adaptive Dynamic Sensing Interface”, ACM/IEEE International Symposium on Low Power Electronics and Design, August 10-12, 2020 [pdf]
  19. [GLSVLSI’20] Shaahin Angizi, Wei Zhang and Deliang Fan, “Exploring DNA Alignment-in-Memory Leveraging EmergingSOT-MRAM”, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), September 7-9, 2020 (invited) [pdf]
  20. [GLSVLSI’20] Adnan Siraj Rakin, Zhezhi He, Li Yang, Yanzhi Wang, Liqiang Wang, Deliang Fan, “Robust Sparse Regularization: Simultaneously Optimizing Neural Network Robustness and Compactness”, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), September 7-9, 2020 (invited) [pdf]
  21. [GLSVLSI’20] Baogang Zhang, Necati Uysal, Deliang Fan and Rickard Ewetz, “Redundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead”, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), September 7-9, 2020 [pdf]
  22. [GLSVLSI’20] Dayane Reis, Di Gao, Shaahin Angizi, Xunzhao Yin, Deliang Fan, Michael Niemier, Cheng Zhuo and X. Sharon Hu, “Modeling and benchmarking computing-in-memory for design space exploration”, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), September 7-9, 2020 (invited) [pdf]
  23. [CVPR’20]  Adnan Siraj Rakin, Zhezhi He and Deliang Fan, “TBT: Targeted Neural Network Attack with Bit Trojan,” 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), June 16-18, 2020, Seattle, Washington, USA [pdf] [open source code]  
  24. [CVPR’20]  Zhezhi He,Adnan Siraj Rakin, Jingtao Li, Chaitali Chakrabarti and Deliang Fan, “Defending and Harnessing the Bit-Flip based Adversarial Weight Attack,” 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), June 16-18, 2020, Seattle, Washington, USA [pdf] [open source code]  
  25. [DAC’20] Li Yang, Zhezhi He, Yu Cao and Deliang Fan. “Non-uniform DNN Structured Subnets Sampling for Dynamic Inference”. In: 57th Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020. [pdf]
  26. [DAC’20] Shaahin Angizi, Naima Ahmed Fahmi, Wei Zhang and Deliang Fan, “PIM-Assembler: A Processing-in-Memory Platform for Genome Assembly” In: 57th Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020. [pdf]
  27. [DAC’20] Jingtao Li, Adnan Siraj Rakin, Yan Xiong, Liangliang Chang, Zhezhi He, Deliang Fan, and Chaitali Chakrabarti. “Defending Bit-Flip Attack through DNN Weight Reconstruction”. In: 57th Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020. [pdf]
  28. [AAAI’20] Li Yang, Zhezhi He and Deliang Fan, “Harmonious Coexistence of Structured Weight Pruning and Ternarization for Deep Neural Networks,” Thirty-Fourth AAAI Conference on Artificial Intelligence (AAAI), Feb. 7-12 2020, New York, USA (spotlight) [pdf]
  29. [DATE’20] Shaahin Angizi, Jiao Sun, Wei Zhang and Deliang Fan, “PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment,” Design, Automation and Test in Europe (DATE), 09-13 March 2020, ALPEXPO, Grenoble, France [pdf]
  30. [ASPDAC’20] Li Yang, Shaahin Angizi, Deliang Fan, “A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 13-16, 2020, Beijing, China [pdf]  
  31. [ASPDAC’20] Baogang Zhang, Necati Uysal, Deliang Fan, Rickard Ewetz, “Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 13-16, 2020, Beijing, China [pdf]
  32. [ICCV’19] Adnan Siraj Rakin* , Zhezhi He*, Deliang Fan, “Bit-Flip Attack: Crushing Neural Network with Progressive Bit Search,” IEEE International Conference on Computer Vision, Seoul, Korea, Oct 27 – Nov 3, 2019 [pdf] (* The first two authors contributed equally) [open source code]
  33. [ICCAD’19] Shaahin Angizi and Deliang Fan, “ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 4-7 November 2019, Westminster, CO [pdf]
  34. [NANOARCH’19] Shaahin Angizi and Deliang Fan, “Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach?,” IEEE/ACM International Symposium on Nanoscale Architectures, 17-19 July 2019, Qingdao, CHINA [pdf]
  35. [ISVLSI’19] Shaahin Angizi, Zhezhi He, Dayane Reis, Xiaobo Sharon Hu, Wilman Tsai, Shy Jay Lin and Deliang Fan, “Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?,” IEEE Computer Society Annual Symposium on VLSI, 15 – 17 July 2019, Miami, Florida, USA (invited)[pdf]
  36. [ISVLSI’19] Adnan Siraj Rakin and Deliang Fan, “Defense-Net: Defend Against a Wide Range of Adversarial Attacks through Adversarial Detector,” IEEE Computer Society Annual Symposium on VLSI, 15 – 17 July 2019, Miami, Florida, USA [pdf]
  37. [Dagstuhl Report’19] Deliang Fan, “Cognitive Computing-in-Memory: Circuit to Algorithm,” Dagstuhl Seminar 19152, Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing, Germany, 2019 [pdf]
  38. [DRC’19] Durjoy Dev, Adithi Krishnaprasad, Zhezhi He, Sonali Das, Mashiyat Sumaiya Shawkat, Madison Manley, Olaleye Aina, Deliang Fan, Yeonwoong Jung and Tania Roy, “Artificial Neuron using Ag/2D-MoS2/Au Threshold Switching Memristor,” 77th Device Research Conference, 23 – 26 June 2019, University of Michigan, Ann Arbor [pdf]
  39. [CVOPS’19] Yifan Ding, Liqiang Wang, Huan Zhang, Jinfeng Yi, Deliang Fan, and Boqing Gong, “Defending Against Adversarial Attacks Using Random Forests,” Workshop on The Bright and Dark Sides of Computer Vision: Challenges and Opportunities for Privacy and Security, June 16-20, 2019, Long Beach, CA, USA [pdf]
  40. [CVPR’19] Zhezhi He*, Adnan Siraj Rakin* and Deliang Fan, “Parametric Noise Injection: Trainable Randomness to Improve Deep Neural Network Robustness against Adversarial Attack,” Conference on Computer Vision and Pattern Recognition (CVPR), June 16-20, 2019, Long Beach, CA, USA (* The first two authors contributed equally) [pdf] [code in GitHub]
  41. [CVPR’19] Zhezhi He and Deliang Fan, “Simultaneously Optimizing Weight and Quantizer of Ternary Neural Network using Truncated Gaussian Approximation,” Conference on Computer Vision and Pattern Recognition (CVPR), June 16-20, 2019, Long Beach, CA, USA [pdf]
  42. [GLSVLSI’19] Shaahin Angizi and Deliang Fan, “GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing,” ACM Great Lakes Symposium on VLSI(GLSVLSI), May 9-11, 2019, Washington, D.C. USA ( –Best Paper Award–[pdf]
  43. [GLSVLSI’19] Li Yang, Zhezhi He and Deliang Fan, “Binarized Depthwise Separable Neural Network for Object Tracking in FPGA,” ACM Great Lakes Symposium on VLSI(GLSVLSI), May 9-11, 2019, Washington, D.C. USA [pdf]
  44. [DAC’19] Shaahin Angizi, Jiao Sun, Wei Zhang and Deliang Fan, “AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM,” Design Automation Conference (DAC), June 2-6, 2019, Las Vegas, NV, USA [pdf]
  45. [DAC’19] Zhezhi He, Jie Lin, Rickard Ewetz, Jiann-Shiun Yuan and Deliang Fan, “Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping,” Design Automation Conference (DAC), June 2-6, 2019, Las Vegas, NV, USA [pdf] [open source code]
  46. [ISQED’19] Arman Roohi, Shaahin Angizi, Deliang Fan and Ronald F DeMara, “Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency and Power-Intermittency Resilience,” The 20th International Symposium on Quality Electronic Design (ISQED), March 6-7, 2019, Santa Clara, CA, USA ( –Best Paper Candidate–)
  47. [DATE’19] Shaahin Angizi, Jiao Sun, Wei Zhang and Deliang Fan, “GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM,” Design, Automation and Test in Europe (DATE), March 25-29, 2019, Florence, Italy. [pdf]
  48. [WACV’19] Zhezhi He, Boqing Gong, Deliang Fan, “Optimize Deep Convolutional Neural Network with Ternarized Weights and High Accuracy,” IEEE Winter Conference on Applications of Computer Vision, January 7-11, 2019, Hawaii, USA [pdf][open source code]
  49. [ASPDAC’19] Shaahin Angizi, Zhezhi He and Deliang Fan, “ParaPIM: A Parallel Processing-in-Memory Accelerator for Binary-Weight Deep Neural Networks,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 21-24, 2019, Tokyo, Japan [pdf]
  50. [ASPDAC’19] Baogang Zhang, Necati Uysal, Deliang Fan, Rickard Ewetz, “Handling Stuck-at-faults in Memristor Crossbar Arrays using Matrix Transformations,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 21-24, 2019, Tokyo, Japan [pdf]( –Best Paper Candidate–)
  51. [ICCD’18] Adnan Siraj Rakin, Shaahin Angizi, Zhezhi He and Deliang Fan, “PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks,” IEEE International Conference on Computer Design (ICCD) , Oct. 7-10, 2018, Orlando, FL, USA [pdf]
  52. [ICCAD’18] Shaahin Angizi, Zhezhi He and Deliang Fan, “DIMA: A Depthwise CNN In-Memory Accelerator,” IEEE/ACM International Conference on Computer Aided Design, Nov. 5-8, 2018, San Diego, CA, USA [pdf]
  53. [ISLPED’18] Li Yang, Zhezhi He and Deliang Fan, “A Fully Onchip Binarized Convolutional Neural Network FPGA Implementation with Accurate Inference,” ACM/IEEE International Symposium on Low Power Electronics and Design, July 23-25, 2018, Bellevue, Washington, USA [pdf]
  54. [ISVLSI’18] Zhezhi He, Shaahin Angizi, Adnan Siraj Rakin and Deliang Fan, “BD-NET: A Multiplication-less DNN with Binarized Depthwise Separable Convolution,” IEEE Computer Society Annual Symposium on VLSI, July 9-11, 2018, Hong Kong, CHINA [pdf] (–Best Paper Award–)
  55. [ISVLSI’18] Zhezhi He, Shaahin Angizi and Deliang Fan, “Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM,” IEEE Computer Society Annual Symposium on VLSI, July 9-11, 2018, Hong Kong, CHINA (invited) [pdf]
  56. [GLSVLSI’18] Shaahin Angizi, Zhezhi He, Yu Bai, Jie Han, Mingjie Lin and Deliang Fan, “Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Network,” ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, IL, USA, May 23-25, 2018 (invited) [pdf]
  57. [DAC’18] Shaahin Angizi*, Zhezhi He*, Adnan Siraj Rakin and Deliang Fan, “CMP-PIM: An Energy-Efficient Comparator-based Processing-In-Memory Neural Network Accelerator,” IEEE/ACM Design Automation Conference (DAC), June 24-28, 2018, San Francisco, CA, USA (* The first two authors contributed equally) [pdf]
  58. [DAC’18] Shaahin Angizi, Zhezhi He and Deliang Fan, “PIMA-Logic: A Novel Processing-in-Memory Architecture for Highly Flexible and Energy-Efficient Logic Computation, ” IEEE/ACM Design Automation Conference (DAC), June 24-28, 2018, San Francisco, CA, USA [pdf]
  59. [WACV’18] Y. Ding, L. Wang, D. Fan and B. Gong “A Semi-Supervised Two-Stage Approach to Learning from Noisy Labels,” IEEE Winter Conference on Applications of Computer Vision, March 12-14, 2018, Stateline, NV, USA [pdf]
  60. [ASPDAC’18] F. Parveen, Z. He, S. Angizi and D. Fan, “HieIM: Highly Flexible In-Memory Computing using STT MRAM,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 22-25, 2018, Jeju Island, Korea [pdf]
  61. [ASPDAC’18] S. Angizi, Z. He, F. Parveen and D. Fan, “IMCE: Energy-Efficient Bit-Wise In-Memory Convolution Engine for Deep Neural Network,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 22-25, 2018, Jeju Island, Korea [pdf]
  62. [ICCD’17] Z. He, S. Angizi and D. Fan, “Exploring STT-MRAM based In-Memory Computing Paradigm with Application of Image Edge Extraction,” IEEE International Conference on Computer Design (ICCD) , Nov. 5-8, 2017, Boston, MA [pdf]
  63. [ICCD’17] D. Fan and S. Angizi “Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM,” IEEE International Conference on Computer Design (ICCD) , Nov. 5-8, 2017, Boston, MA [pdf]
  64. [NCAMA’17] S. Angizi and D. Fan , “IMC: Energy-Efficient In-Memory Convolver for Accelerating Binarized Deep Neural Network,” Neuromorphic Computing Symposium: Architectures, Models, and Applications , July 17-19, 2017, Knoxville, Tennessee [pdf]
  65. [ICCAD’17] M. Yang, J. Hayes, D. Fan and W. Qian, “Design of Accurate Stochastic Number Generators with Noisy Emerging Devices for Stochastic Computing,” IEEE/ACM International Conference on Computer Aided Design, Nov 13-16, Irvin, CA [pdf]
  66. [ISLPED’17] F. Parveen, S. Angizi, Z. He and D. Fan , “Low Power In-Memory Computing based on Dual-Mode SOT-MRAM,” IEEE/ACM International Symposium on Low Power Electronics and Design, July 24-26, 2017, Taipei, Taiwan [pdf]
  67. [NANOARCH’17] Z. He, S. Angizi, F. Parveen and D. Fan , “High Performance and Energy-Efficient In-Memory Computing Architecture based on SOT-MRAM,” IEEE/ACM International Symposium on Nanoscale Architectures , July 25-26, 2017, Newport, USA [pdf]
  68. [ISVLSI’17] D. Fan, S. Angizi and Z. He, “In-Memory Computing with Spintronic Devices,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany (invited) [pdf]
  69. [ISVLSI’17] S. Angizi, Z. He, F. Parveen and D. Fan, “RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany [pdf]
  70. [ISVLSI’17] F. Parveen, Z. He, S. Angizi and D. Fan, “Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany [pdf] ( –Best Paper Award–)
  71. [MWSCAS’17] D. Fan, Z. He and S. Angizi, “Leveraging Spintronic Devices for Ultra-Low Power In-Memory Computing: Logic and Neural Network,” 60th IEEE International Midwest Symposium on Circuits and Systems, Aug. 6-9, 2017, Boston, MA, USA (invited) [pdf]
  72. [ISCAS’17] F. Parveen, S. Angizi, Z. He and D. Fan, “Hybrid Polymorphic Logic Gate Using 6 Terminal Magnetic Domain Wall Motion Device,” IEEE International Symposium on Circuits & Systems (ISCAS), Baltimore, MD, USA, May 28-31, 2017 [pdf]
  73. [GLSVLSI’17] Z. He, S. Angizi, F. Parveen, and D. Fan, “Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-Memory Data Encryption”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017 [pdf]
  74. [GLSVLSI’17] S. Angizi, Z. He, and D. Fan, “Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017 [pdf]
  75. [GLSVLSI’17] Q. Alasad, J. Yuan, and D. Fan, “Leveraging All-Spin Logic to Improve Hardware Security”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017 [pdf]
  76. [DATE’17] Z. He, D. Fan, “A Tunable Magnetic Skyrmion Neuron Cluster for Energy Efficient Artificial Neural Network,” Design, Automation and Test in Europe (DATE), Lausanne, Switzerland, 27-31 March, 2017 [pdf]
  77. [ISQED’17] S. Angizi, Z. He, R. DeMara and D. Fan, “Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing,” 18th International Symposium on Quality Electronic Design(ISQED), Santa Clara, CA, USA, 13-15 March, 2017[pdf]
  78. [ISLPED’16] Z. He and D. Fan, “A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator”, International Symposium on Low Power Electronics and Design (ISLPED), San Francisco, CA, Aug. 8-10, 2016[pdf]
  79. [NANOARCH’16] D. Fan, “Low Power In-Memory Computing Platform with Four Terminal Magnetic Domain Wall Motion Devices”, IEEE/ ACM International Symposium on Nanoscale Architectures, , Beijing, China, July 18-20, 2016 [pdf]
  80. [GLSVLSI’16] D. Fan, “ Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate”, 26th GLSVLSI, Boston, Massachusetts, May 18-20, 2016[pdf]
  81. [IJCNN’16] C. Liyanagedera, K. Yogendra, K. Roy and D. Fan, “ Spin Torque Nano-Oscillator based Oscillatory Neural Network”, 2016 IEEE International Joint Conference on Neural Network (IJCNN), Vancouver, Canada, July 24-29, 2016[pdf]
  82. [ASPDAC’16] K. Yogendra, D. Fan, Y. Shim, M. Koo, and K. Roy, “ Computing with Coupled Spin Torque Nano Oscillators”, 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 25-28, 2016[pdf]
  83. [ASPDAC’16] A. Sengupta, K. Yogendra, D. Fan and K. Roy, “Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses”, 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 25-28, 2016[pdf]
  84. [DATE’14] K. Roy, M. Sharad, D. Fan and K. Yogendra, “Brain-inspired computing with spin torque devices”, Design, Automation & Test in Europe (DATE), 2014. (invited tutorial)[pdf]
  85. [ISVLSI’14] K. Roy, M. Sharad, D. Fan and K. Yogendra, “Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, July 9-11, 2014 (special session paper)[pdf]
  86. [DAC’13] M. Sharad, D. Fan, and K. Roy, “Ultra Low Power Associative Computing With Spin Neurons and Resistive Crossbar Memory,” IEEE/ACM Design Automation Conference (DAC), Austin, TX, June 2-6, 2013[pdf]
  87. [ISLPED’13] K. Roy, M. Sharad, D. Fan, and K. Yogendra, “Beyond Charge-Base Computing: Boolean and Non Boolean computing Using spin Devices,” International Symposium on Low Power and Design (ISLPED), 2013. (invited tutorial)[pdf]
  88. [ICCAD’13] K. Roy, M. Sharad, D. Fan, and K. Yogendra, “Exploring Boolean and Non Boolean Computing Using Spin torque Switches” International Conference on Computer-Aided Design (ICCAD), 2013. (invited tutorial)[pdf]
  89. [ISQED’13] M. Sharad, D. Fan, and K. Roy, “Low Power and Compact Mixed-Mode Signal Processing Hardware using Spin-Neurons,” IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, March 4-6, 2013[pdf]
  90. [E3S’13] M. Sharad, D. Fan, K. Yogendra, and K. Roy, “Ultra-Low Power Neuromorphic Computing with Spin-Torque Devices,” 3rd Berkeley Symposium on Energy Efficient Electronic Systems, 2013[pdf]